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RT8278 1 ds8278-02 march 2011 www.richtek.com note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. pin configurations (top view) applications dsl modem for adsl2+ standard distributed power systems pre-regulator for linear regulators sop8 (exposed pad) 2a, 24v, 3mhz step-down converter general description the RT8278 is a high voltage buck converter that can support an input voltage range from 4.5v to 24v with output current up to 2a. current mode operation provides fast transient response and eases loop stabilization. the chip provides protection functions such as cycle-by- cycle current limiting and thermal shutdown protection. in shutdown mode, the regulator only draws 25 a of supply current. the RT8278 is available in a sop-8 (exposed pad) package. features wide operating input range : 4.5v to 24v adjustable output voltage range : 0.8v to 15v output current up to 2a 25 a low shutdown current high efficiency up to 90% at 2.2mhz programmable frequency : 220khz to 3mhz internal soft-start stable with low esr output ceramic capacitors thermal shutdown protection cycle-by-cycle over current protection rohs compliant and halogen free typical application circuit boot vin sw gnd rt en fb comp gnd 2 3 4 5 6 7 8 9 ordering information marking information RT8278 gspymdnn RT8278gsp : product number ymdnn : date code 4.5v to 24v nc vin en gnd boot fb sw 7 5 2 3 1 l 2.2h 10nf 22f r1 31.6k r2 10k v out 3.3v/2a 10f chip enable v in RT8278 d b220a rt 8 r rt 24k comp c c 1nf r c 36k c p 6 4, 9 (exposed pad) c boot c out c in package type sp : sop-8 (exposed pad-option 1) RT8278 lead plating system g : green (halogen free and pb free)
RT8278 2 ds8278-02 march 2011 www.richtek.com functional pin description pin no. pin name pin function 1 boot bootstrap power pin. boot supplies the drive for the high side n-mosfet switch. connect a 10nf or greater capacitor from sw to boot to power the high side switch. 2 vin supply input. v in supplies the power to the ic, as well as the step-down converter switches. drive v in with a 4.5v to 24v power source. bypass v in to gnd with a suitably large capacitor to eliminate noise on the input to the ic. 3 sw switch node. sw is the switching node that supplies power to the output. connect the output lc filter from sw to the output load. note that a capacitor is required from sw to boot to power the high side switch. 4, 9 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 5 fb feedback input. fb senses the output voltage to regulate. drive fb with a resistive voltage divider from the output voltage. 6 comp compensation node. comp is used to compensate the regulation control loop. connect a series rc network from comp to gnd to compensate the regulation control loop. in some cases, an additional capacitor from comp to gnd is required. 7 en enable input. en is a digital input that turns the regulator on or off. drive en higher than 1.4v to turn on the regulator, lower than 0.4v to turn off. for automatic startup, leave en unconnected. 8 rt oscillator resistor input. connecting a resistor to ground from this pin sets the switching frequency. table 1. recommended component selection for f sw = 2.2mhz v out (v) r1 (k ) r2 (k ) r c (k ) c c (nf) l ( h) c out ( f) 10 115 10 82 0.56 8.2 22 8 91 10 68 0.56 6.8 22 5 52.3 10 56 1.8 4.7 22 3.3 31.6 10 36 1 2.2 22 2.5 21.5 10 27 1.2 2 22 1.8 12.4 10 20 1.8 1.5 22 1.5 8.87 10 16 3.3 1.5 22 1.2 4.99 10 24 1 1 22
RT8278 3 ds8278-02 march 2011 www.richtek.com function block diagram v a + - + - + - uv comparator oscillator foldback control 0.4v internal regulator + - 1v shutdown comparator current sense amplifier boot vin gnd sw fb en comp 3v 10k v a v cc 1a slope comp current comparator + - ea 0.8v + - 0.8v s r q q rt
RT8278 4 ds8278-02 march 2011 www.richtek.com electrical characteristics parameter symbol test conditions min typ max unit feedback reference voltage v fb 4.5v v in 24v 0.784 0.8 0.816 v upper switch on resistance r ds(on )1 -- 0. 18 -- lower switch on resistance r ds(on )2 -- 10 -- upper switch leakage i leak v en = 0v, v sw = 0v -- 0 10 a current limit i lim duty = 90%, v boo t ? v sw = 4.8v -- 3 -- a current sense transconductance output current to c omp pin vo lta ge g cs -- 1.8 -- a/v error amplifier transconductance g ea i c = 10 a -- 920 -- a/v oscillator frequency f sw r rt = 24k -- 2.2 -- mhz short circuit frequency v fb = 0v, r rt = 24k -- 550 -- khz under voltage lockout threshold rising v uvlo -- 4.2 -- v under voltage lockout threshold h ysteresis v uv lo -- 430 -- mv maximum duty c ycle d max v fb = 0. 7v, r rt = 24k -- 65 -- % minimum on time t on -- 70 -- ns (v in = 12v, t a = 25 c, unless otherwise specified) recommended operating conditions (note 4) supply input voltage, v in ----------------------------------------------------------------------------------- 4.5v to 24v junction temperature range ------------------------------------------------------------------------------- ? 40 c to 125 c ambient temperature range ------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) v in ---------------------------------------------------------------------------------------------------------------- ? 0.3v to 26v sw --------------------------------------------------------------------------------------------------------------- ? 0.3v to (v in + 0.3v) boot ----------------------------------------------------------------------------------------------------------- ( v sw ? 0.3v) to (v sw + 6v) all other pins ------------------------------------------------------------------------------------------------- ? 0.3v to 6v power dissipation, p d @ t a = 25 c sop-8 (exposed pad) -------------------------------------------------------------------------------------- 1.333w package thermal resistance (note 2) sop-8 (exposed pad), ja --------------------------------------------------------------------------------- 75 c/w sop-8 (exposed pad), jc -------------------------------------------------------------------------------- 28 c/w lead temperature (soldering, 10 sec.) ------------------------------------------------------------------ 260 c junction temperature ---------------------------------------------------------------------------------------- 150 c storage temperature range ------------------------------------------------------------------------------- ? 65 c to 150 c esd susceptibility (note 3) hbm (human body mode) --------------------------------------------------------------------------------- 2kv mm (ma chine mode) ----------------------------------------------------------------------------------------- 200v to be continued
RT8278 5 ds8278-02 march 2011 www.richtek.com parameter symbol test conditions min typ max unit logic-high v ih 1.4 -- -- en t hresh old volta ge logic-low v il -- -- 0.4 v enable pull up current -- 1 -- a quiescent current i q v en = 2v, v fb = 1v -- 0.8 1 ma shutdown current i shdn v en = 0v -- 25 -- a thermal shutdown -- 150 -- c note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in natural convection at t a = 25 c on a high effective thermal conductivity four-layer test board of jedec 51-7 thermal measurement standard. the measurement case position of jc is on the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
RT8278 6 ds8278-02 march 2011 www.richtek.com typical operating characteristics output voltage vs. input voltage 3.310 3.315 3.320 3.325 3.330 3.335 3.340 3.345 3.350 3.355 3.360 3.365 3.370 0 5 10 15 20 25 input voltage (v) output voltage (v) i out = 0a output voltage vs. output current 4.85 4.88 4.91 4.94 4.97 5.00 5.03 5.06 5.09 5.12 0.0 0.4 0.8 1.2 1.6 2.0 output current (a) output voltage (v) v in = 19v v in = 12v quiescent current vs. temperature 0.60 0.64 0.68 0.72 0.76 0.80 0.84 0.88 -50 -25 0 25 50 75 100 125 temperature (c) quiescent current (ma ) v in = 12v, r rt = open reference voltage vs. temperature 0.70 0.74 0.78 0.82 0.86 0.90 -50 -25 0 25 50 75 100 125 temperature (c) reference voltage (v) v in = 12v, i out = 0a efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.0 0.4 0.8 1.2 1.6 2.0 output current (a) efficiency (%) v in = 12v, v out = 3.3v, f sw = 2.2mhz efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.0 0.4 0.8 1.2 1.6 2.0 output current (a) efficiency (%) v in = 19v v in = 12v v out = 5v, f sw = 2.2mhz
RT8278 7 ds8278-02 march 2011 www.richtek.com switching frequency vs. temperature 1.8 1.9 2.0 2.1 2.2 2.3 2.4 -50 -25 0 25 50 75 100 125 temperature (c) switching frequency (mhz) 1 v in = 12v, v out = 3.3v, l out = 0.3a, r rt = 24k load transient response time (100 s/div) v out (100mv/div) i out (1a/div) v in = 12v, v out = 3.3v l out = 0 to 2a, f sw = 2.2mhz current limit vs. duty cycle 1.5 1.9 2.3 2.7 3.1 3.5 3.9 4.3 0 20406080100 duty cycle (%) current limit (a) f sw = 2.2mhz f sw = 400khz current limit vs. temperature 1.5 2.0 2.5 3.0 3.5 4.0 4.5 -50 -25 0 25 50 75 100 125 temperature (c) peak current (a ) v in = 12v, v out = 3.3v, f sw = 2.2mhz output ripple voltage time (200ns/div) v out (10mv/div) v sw (10v/div) i l (1a/div) v in = 12v, v out = 3.3v i out = 2a, f sw = 2.2mhz v in = 12v, v out = 3.3v i out = 1 to 2a, f s = 2.2mhz load transient response time (100 s/div) v out (100mv/div) i out (1a/div) v in = 12v, v out = 3.3v i out = 1a to 2a, f sw = 2.2mhz
RT8278 8 ds8278-02 march 2011 www.richtek.com v in = 12v, v out = 3.3v, i out = 2a, f s = 2.2mhz v in = 12v, v out = 3.3v, i out = 2a, f s = 2.2mhz power off from en time (40 s/div) v en (2v/div) i l (2a/div) v out (1v/div) v in = 12v, v out = 3.3v, i out = 2a, f sw = 2.2mhz power on from en time (400 s/div) v en (2v/div) i l (2a/div) v out (1v/div) v in = 12v, v out = 3.3v, i out = 2a, f sw = 2.2mhz
RT8278 9 ds8278-02 march 2011 www.richtek.com application information the RT8278 is an asynchronous high voltage buck converter that supports an input voltage range from 4.5v to 24v with output current up to 2a. output voltage setting the resistive voltage divider allows the fb pin to sense the output voltage as shown in figure 1. RT8278 gnd fb r1 r2 v out figure 1. output voltage setting operating frequency selection of the operating frequency is a trade off between efficiency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequency improves efficiency by reducing internal gate charge and switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. the operating frequency of the RT8278 is determined by an external resistor that is connected between the rt pin and ground. the value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator. selection of the rt resistor value can be determined by examining the curve below in figure3. although frequencies as high as 3mhz are available, the minimum on-time of the RT8278 imposes a limit on the operating duty cycle. figure 4 shows the examples of minimum on-time constraint for output voltages 3.3v and 1.8v. it is recommended to operate the RT8278 in the region under the corresponding vout curve. except the minimum on-time constraint, the limit of maximum duty also needs to be considered. in ideal case, the duty cycle of the RT8278 can be calculated by below equation, but in practical case it will be higher than the calculation result since all the components in a converter circuit are not ideal. figure 5 shows an example for the limit of maximum duty. with 5v input voltage, the 3.3v output voltage of the RT8278 becomes out of regulation when the output current is increased. however, when the input voltage is changed to 12v, the 3.3v output voltage of the RT8278 remains in regulation even with 2a output current. according to equation below, the duty cycle is 0.67 for the RT8278 operated with 5v input voltage and 3.3v output voltage in 2.2mhz switching frequency. the ideal case duty cycle calculation is already over the limit of maximum duty(65%). thus, it is obvious that the RT8278 can't support 2a output current in such conditions : sw duty cycle 1 0.15 x f (mhz) =? the output voltage is set by an external resistive voltage divider according to the following equation : ?? + ?? ?? out fb r1 v = v1 r2 where v fb is the feedback reference voltage (0.8v typ.). external bootstrap diode connect a 10nf low esr ceramic capacitor between the boot pin and sw pin. this capacitor provides the gate driver voltage for the high side mosfet. it is recommended to add an external bootstrap diode between an external 5v voltage source and the boot pin for efficiency improvement when input voltage is lower than 5.5v or duty cycle is higher than 65% .the bootstrap diode can be a low cost one such as in4148 or bat54. the external voltage source must be fixed at 5v and can be provided from the system or the output of the RT8278. sw boot 5v RT8278 10nf figure 2. external bootstrap diode
RT8278 10 ds8278-02 march 2011 www.richtek.com chip enable operation the en pin is the enable input. pull the en pin low (<0.4v) to shutdown the device. during shutdown mode, the RT8278 quiescent current drops to lower than 25 a. drive the en pin high (>1.4v, < 5.5v), to turn on the device. if the en pin is open, it will be pulled high by the internal circuit. for external timing control (e.g.rc), the en pin can also be externally pulled high by adding a 100k or greater resistor from the vin pin (see figure 6). in some cases, the output voltage of the RT8278 may still be under uvp threshold when soft-start finishes. then the RT8278 will restart again and the output voltage of the RT8278 will rise to the regulation voltage. this phenomenon often happens in high frequency operation and with slow rising input voltage. it can easily be solved by adding a voltage divider on the en pin. the RT8278 will be enabled when the input voltage rises close to the nominal input voltage. inductor selection the inductor value and operating frequency determine the ripple current according to a specific input and output voltage. the ripple current i l increases with higher v in and decreases with higher inductance : out out sw l(max) in(max) vv l = x 1 f x i v ???? ? ???? ???? the inductor's current rating (defined by that which causes a temperature rise from 25 c ambient to 40 c) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. refer to table 2 for the suggested inductor selection. figure 5. limit of maximum duty figure 4. minimum on-time constraint to input voltage minimum on-time constraint 0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 1000 1400 1800 2200 2600 3000 switching frequency (khz) input voltage (v) v out = 3.3v v out = 1.8v figure 3. switching frequency vs. r rt switching frequency vs. r rt 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 0 200 400 600 800 1000 r rt (k ? ) switching frequency (khz) 1 r rt (k ) out out l sw in vv i = x1 f x l v ??? ? ? ??? ? ??? ? having a lower ripple current reduces not only the esr losses in the output capacitors but also the output voltage ripple. higher frequency combined with smaller ripple current is necessary to achieve high efficiency operation. however, it requires a large inductor to achieve this goal. for the ripple current selection, setting the maximum val ue of the ripple current i l = 0.24(i max ) is a reasonable starting point. the large st ripple current occurs at the highest v in . to guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : output voltage vs. load current 2.80 2.85 2.90 2.95 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 0.0 0.4 0.8 1.2 1.6 2.0 load current (a) output voltage (v) v in = 5v v in = 12v f sw = 2.2mhz
RT8278 11 ds8278-02 march 2011 www.richtek.com diode selection when the power switch turns off, the path for the current is through the diode connected between the switch output and ground. this forward biased diode must have a minimal voltage drop and recovery time. schottky diodes are recommended and should be able to handle those current. the reverse voltage rating of the diode should be greater than the maximum input voltage, and the current rating should be greater than the maximum load current. for details, please refer to table 3. this formula has a maximum at v in = 2v out , where i rms = i out / 2. this simple worst-case condition is commonly used for design. choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. out l out 1 viesr 8fc ?? ?? + ?? ?? the output ripple will be highest at the maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirement. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr value. however, it provides lower capacitance density than other types. although tantalum capacitors have the highest capacitance density, it is important to only use types that pass the surge test for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr. however, it can be used in cost sensitive applications for ripple current rating and long term reliability considerations. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. nevertheless, high value low cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. table2. suggested inductors for typical application circuit component supplier series dimensions (mm) tdk vlc6045 6 x 6 x 4.5 tdk slf12565 12.5 x 12.5 x 6.5 taiyo yuden nr8040 8 x 8 x 4 component supplier series v rrm (v) i out (a) package diodes b330a 30 3 sma diodes b220a 20 2 sma panjit sk22 20 2 do-214aa panjit sk23 30 2 do-214aa table 3. suggested diode out in rms out(max) in out v v i = i 1 vv ? c in and c out selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the high side mosfet. to prevent large ripple current, a low esr input capacitor sized for the maximum rms current should be used. the rms current is given by : for the input capacitor, one 10 f low esr ceramic capacitors is recommended. for the recommended capacitor, please refer to table 4 below for more details. the selection of c out is determined by the required esr to minimize voltage ripple. moreover, the amount of bulk capacitance is also a key for c out selection to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by :
RT8278 12 ds8278-02 march 2011 www.richtek.com c c c 1 c f 2r 4 = choose a capacitor that is greater than the above calculation result. the frequency of the zero, which consists of r c and c c, should be lower than one fourth of f c to get a sufficient phase margin. if the zero moves close to f c , the phase margin decreases. in some applications, the output capacitor will be an electrolytic capacitor, not a ceramic capacitor. a zero will be produced by the electrolytic capacitor and its esr. c p can be used to produce a pole with r c to cancel the zero. to calculate c p, follow the equation below : out p c cesr c r = emi consideration since parasitic inductance and capacitance effects in pcb circuitry would cause a spike voltage on the sw pin when the high side mosfet is turned-on/off, this spike voltage on sw may impact emi performance in the system. in order to enhance emi performance, there are two methods to suppress the spike voltage. one is to place an r-c snubber between sw and gnd and place them as close as possible to the sw pin (see figure 6). another method is to add a resistor in series with the bootstrap capacitor, c boot . but this method will decrease the driving capability to the high side mosfet. it is strongly recommended to reserve the r-c snubber during pcb layout for emi improvement. moreover, reducing the sw trace area and keeping the main power in a small loop will be helpful for emi performance. for detailed pcb layout guide, please refer to the section on layout consideration. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load (esr) and c out also begins to be charged or discharged generating a feedback error signal for the regulator to return v out to its steady state value. during this recovery time, v out can be monitored for overshoot or ringing to indicate any stability problem. compensation parameters the switching frequency of RT8278 can be programmed from free running frequency to 3mhz. table 1 only lists the recommended compensation parameters for 2.2mhz switching frequency. optimized compensation parameters for other switching frequency can also be determined through below procedures. the first step is to decide the crossover frequency, fc. in general, the crossover frequency is one tenth of the switching frequency. then, rc can be obtained through the following equation : out c out c cs ea fb 2c fv r ggv = where g cs is current sensetransconductance = 1.8 (a/v) g ea is error amplifier tansconductance = 920 ( a/v) once the value of rc has been determined, the value of cc can be obtained by the following equation : 4.5v to 24v nc vin en gnd boot fb sw 7 5 2 3 1 l 2.2h 10nf 22f r1 31.6k r2 10k v out 3.3v/2a 10f chip enable v in RT8278 d b220a rt 8 r rt 24k comp c c 1nf r c 36k c p 6 4, 9 (exposed pad) c boot c out c in r en * c en * r boot * r s * c s * * : optional figure 6. reference circuit with snubber and enable timing control
RT8278 13 ds8278-02 march 2011 www.richtek.com thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications of the RT8278, the maximum junction temperature is 125 c and t a is the ambient temperature. the junction to ambient thermal resistance, ja , is layout dependent. for sop-8 (exposed pad) packages, the thermal resistance, ja , is 75 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a =25 c can be calculated by the following formulas : p d(max) = (125 c ? 25 c) / (75 c/w) = 1.333w (min. copper area pcb layout) p d(max) = (125 c ? 25 c) / (49 c/w) = 2.04w (70mm 2 copper area pcb layout) the thermal resistance, ja , of sop-8 (exposed pad) is determined by the package architectural design and the pcb layout design. the package architectural design is fixed. however, it's possible to increase thermal performance via better pcb layout copper design. the thermal resistance, ja , can be decreased by adding copper area under the exposed pad of the sop-8 (exposed pad) package. as shown in figure 7, the amount of copper area to which the sop-8 (exposed pad) is mounted on affects thermal performance. when mounted to the standard sop-8 (exposed pad) (figure 7a), ja is 75 c/w. adding copper area under the sop-8 (exposed pad) (figure 7b) reduces ja to 64 c/w. further increasing the copper area to 70mm 2 (figure 7e) will reduce ja to 49 c/w. the maximum power dissipation depends on operating ambient temperature for fixed t j (max) and thermal resistance, ja . for the RT8278 packages, the derating curves in figure 8 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 7. themal resistance vs. copper area layout design (a) copper area = (2.3 x 2.3) mm 2 , ja = 75 c/w (b) copper area = 10mm 2 , ja = 64 c/w (c) copper area = 30mm 2 , ja = 54 c/w (d) copper area = 50mm 2 , ja = 51 c/w (e) copper area = 70mm 2 , ja = 49 c/w
RT8278 14 ds8278-02 march 2011 www.richtek.com figure 8. derating curves for RT8278 package v in v out gnd c in gnd c p c c r c sw d v out c out l r1 r2 input capacitor must be placed as close to the ic as possible. sw should be connected to inductor by wide and short trace. keep sensitive components away from this trace. the feedback components must be connected as close to the device as possible. boot vin sw gnd rt en fb comp gnd 2 3 4 5 6 7 8 9 r s c s gnd r rt figure 9. pcb layout guide layout consideration follow the pcb layout guidelines for optimum performance of the RT8278. ` keep the traces of the main current paths as short and wide as possible. ` place the input capacitor as close as possible to the device pins (vin and gnd). ` sw node experiences high frequency voltage swing and should be kept in a small area. keep analog components away from the sw node to prevent stray capacitive noise pick up. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 0 255075100125 ambient temperature p ower di ss i pat i on (w) ( c) copper area 70mm 2 50mm 2 30mm 2 10mm 2 min.layout four layer pcb ` connect the feedback network behind the output capacitors. keep the loop area small. place the feedback components near the RT8278. ` connect all analog grounds to a common node and then connect the common node to ground behind the output capacitors. ` an example of the pcb layout guide is shown in figure 9 for reference.
RT8278 15 ds8278-02 march 2011 www.richtek.com table 4. suggested capacitors for c in and c out location component supplier part no. capacitance ( f) case size c in murata grm31cr61e106k 10 1206 c in tdk c3225x5r1e106k 10 1206 c in taiyo yuden tmk316bj106ml 10 1206 c out murata grm31cr60j476m 47 1206 c out tdk c3225x5r0j476m 47 1210 c out murata grm32er71c226m 22 1210 c out tdk c3225x5r1c226m 22 1210
RT8278 16 ds8278-02 march 2011 www.richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. preliminary richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 x 2.000 2.300 0.079 0.091 option 1 y 2.000 2.300 0.079 0.091 x 2.100 2.500 0.083 0.098 option 2 y 3.000 3.500 0.118 0.138

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